n-Dimensional modular multiprocessor lattice architecture

Details n-Dimensional modular multiprocessor lattice architecture n-Dimensional modular multiprocessor lattice architecture

1989-05-17

1990-06-12

Shaw, Gareth D.

Boots, shoes, and leggings

364229, 3642291, 3642287, 3642285, 3642327, 3642419, 364244, 3642448, G06F 1516

Patent

active

049338366

ABSTRACT:
A plurality of n-dimensional modular entities are internally interconnected via as many as n duel port random access memory devices (DPRs), each memory device dedicated solely to the interchange of information between two modular entities in an n-dimensional lattice of modular entities. One or more of the modular entities may itself be a separate multiprocessor architecture.

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patent: 4514807 (1985-04-01), Nogi
patent: 4641238 (1987-02-01), Kneib
patent: 4672535 (1987-06-01), Katzman et al.
patent: 4720780 (1988-01-01), Dolecek
"Concurrent Computers Ideal for Inherently Parallel Problems," Computer Design, Sep. 1, 1985, pp. 99-107 by Asbury et al.

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