N-clock, n-bit-serial multiplier

Details N-clock, n-bit-serial multiplier N-clock, n-bit-serial multiplier

1987-04-14

1989-06-13

Harkcom, Gary V.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

048398470

ABSTRACT:
A bit-serial multiplier has a multi-stage input data register and a multi-tiered tree of multiplexer/adder circuits coupled thereto which produces, at the output of the adder at the top tier of the tree, successive bit serial digital output codes representative of the products of a prescribed digital data code and successive input data codes as the input data codes are sequentially shifted into and through the input data register. By multiplexing the inputs to the adders of the tree to execute either an add function or to bypass data to the output successive output products codes can be generated at a twice the rate required to shift respective input codes into and through the input data register, thereby increasing the effective computational speed of the multiplier. The multiplexing/addition function of each multiplexer/adder involves controllably coupling the contents of selected stages of the input data register to selected adders of the adder tree and intercoupling selected ones of the adders between successive tiers of the adder tree, while effectively bypassing selected others of the adders between successive tiers of the adder tree, for each computational cycle of the adder tree, as the input data code is shifted therethrough. During the clocking of each input data code through the data register, the controllably coupling, intercoupling and bypassing of the adders of the tree is carried out in dependence upon the location of the code within the stages of the data register.

REFERENCES:
patent: 3508038 (1970-04-01), Goldschmidt et al.
patent: 3993890 (1976-11-01), Peled et al.
patent: 4679164 (1987-07-01), Rearick
patent: 4706211 (1987-11-01), Yamazaki et al.

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