N-channel pull-up transistor with reduced body effect

Details N-channel pull-up transistor with reduced body effect N-channel pull-up transistor with reduced body effect

1991-09-16

1993-03-02

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072962, H03K 190175

Patent

active

051912449

ABSTRACT:
A CMOS output buffer circuit employing an N-channel pull-up transistor with reduced body effect includes an N-channel pull-up transistor (N2), an N-channel coupling transistor (N1), and an N-channel discharging transistor (N3). The pull-up transistor has its drain connected to an upper power supply potential (VCC), its source connected to an output node (20), its gate connected to a first internal node (B), and its local substrate connected to a second internal node (A). The coupling transistor has its source connected to the second internal node (A), its drain connected to the source of the pull-up transistor, its gate connected to the first internal node (B), and its local substrate connected to the local substrate of the pull-up transitor (N2). The discharging transistor has its drain connected to the second internal node (A), its source connected to a lower power supply potential (VCC), its gate connected to a third internal node (C), and its local substrate connected to the lower power supply potential (VSS). The coupling transistor and the discharging transistor serve to reduce the body effect on the pull-up transistor (N2) and to provide higher immunity from noise on the upper power supply potential (VCC).

REFERENCES:
patent: 3720848 (1973-03-01), Schmidt, Jr.
patent: 4324991 (1982-04-01), Tamaki
patent: 4473761 (1984-09-01), Peterson

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