Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-03
2001-07-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257S510000, C257S513000, C257S514000, C257S515000, C438S424000, C438S433000, C438S435000, C438S436000
Reexamination Certificate
active
06261920
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an n-channel MOSFET having an STI (Shallow Trench Isolation) structure and a method for manufacturing the same, and more particularly to the improvement of the kink characteristic of an n-channel MOSFET.
Recently, in order to attain the high integration density and high performance of an LSI by miniaturizing elements, an element isolation insulating film of STI structure has been often used instead of an element isolation insulating film formed by the LOCOS (Local Oxidation Of Silicon) method which has been conventionally widely used.
(a) In the LOCOS method, since an SiO
2
film is formed on the element isolation region by thermal oxidation while a film such as an Si
3
N
4
film having good resistance to oxidation is used as a mask, it becomes difficult to enhance the insulation property thereof in the depth direction by making the element isolation film thick and it is impossible to attain a sufficiently long effective element isolation distance owing to miniaturization, and (b) since oxidation proceeds in the end portion of the element isolation region in the thermal oxidation process, a field bird's beak is formed to act as a troublesome obstacle to the miniaturization. On the other hand, in the STI structure, (c) since the pattern dimension is determined by the normal photo-etching process and anisotropic dry etching process, a fine pattern dimension can be attained by use of the high processing technology, and (d) since a long effective element isolation distance can be easily attained in the depth direction by forming a deep trench, for example, it is more advantageous for miniaturization in comparison with the element isolation insulating film formed by the LOCOS method. By the above reasons, in the recent LSI, the element isolation region is formed with the STI structure which is advantageous for miniaturization.
As one example of a conventional semiconductor device having the above STI structure, an n-channel MOSFET and a manufacturing method therefor are explained.
FIG. 1A
is a pattern view,
FIG. 1B
is a cross sectional view taken along the
1
B—
1
B line of FIG.
1
A and
FIG. 1C
is a cross sectional view taken along the
1
C—
1
C line of
FIG. 1A. A
p-well region
12
is formed in the main surface portion of a p-type Si substrate
11
. In the p-well region
12
, n
+
-type diffusion layers used as source/drain regions
13
of the n-channel MOSFET are separately formed. A trench is formed in the main surface portion of the p-type Si substrate
11
and an oxide film (buried oxide film)
14
is filled in the trench to form an element isolation region of STI structure. A gate insulating film
15
is formed on a portion of the substrate
11
which lies between the source and drain regions
13
and a gate electrode
16
is formed on the gate insulating film. An inter-level insulating film (SiO
2
/BPSG)
17
is formed on the main surface of the substrate
11
. Contact plugs
18
are formed in contact holes formed in portions of the inter-level insulating film
17
which correspond to the source/drain regions
13
. Metal wirings used as source/drain electrodes
19
are formed on the inter-level insulating film
17
. The source/drain electrodes
19
are electrically connected to the source/drain regions
13
via the contact plugs
18
, respectively.
Next, a manufacturing method of the n-channel MOSFET shown in
FIGS. 1A
,
1
B and
1
C is explained.
FIGS. 2A
to
8
A are cross sectional views showing the cross sections taken along the
1
B—
1
B line of
FIG. 1A
in the order of the manufacturing steps.
FIGS. 2B
to
8
B are cross sectional views showing the cross sections taken along the
1
C—
1
C line of
FIG. 1A
in the order of the manufacturing steps. First, as shown in
FIGS. 2A and 2B
, the main surface of the p-type Si substrate
11
is subjected to the thermal oxidation process to form an SiO
2
film (buffer film)
21
with a thickness of 10 nm, for example. Then, a polycrystalline Si film
22
with a thickness of approx. 200 nm is deposited and formed on the above film by the LP-CVD method. Further, an SiO
2
film
23
with a thickness of 200 nm is deposited and formed on the above film
22
by the LP-CVD method. Next, a mask (resist pattern)
24
corresponding to the element region is formed on the SiO
2
film
23
by the photo-etching process. The SiO
2
film
23
is etched by the anisotropic dry etching process having a large selective etching ratio with respect to polycrystalline Si with the resist pattern
24
used as a mask.
After this, the resist pattern
24
is separated. Then, the polycrystalline Si film
22
is etched by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to an oxide film with the remaining SiO
2
film
23
used as a mask, further the thermal oxide film (SiO
2
film)
21
is etched, and as a result, the structure shown in
FIGS. 3A and 3B
is obtained.
After this, the Si substrate
11
is etched to the depth of approx. 0.5 &mgr;m by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to an oxide film so as to form a trench
25
used for forming the STI structure as shown in
FIGS. 4A and 4B
.
Then, an SiO
2
film
14
is deposited and formed to the thickness of approx. 1.5 &mgr;m on the entire surface of the resultant semiconductor structure by the LP-CVD method. Next, the SiO
2
film
14
is made flat by the CMP (Chemical Mechanical Polishing) method having a preset selective etching ratio with respect to polycrystalline Si. After the planarization process, the SiO
2
films
14
,
23
are etched by use of NH
4
F or by the dry etching process until the main surface of the polycrystalline Si film
22
is just exposed. As a result, the SiO
2
film is left behind in the trench
25
and the buried oxide film
14
is formed (refer to FIGS.
5
A and
5
B).
Next, the polycrystalline Si film
22
is etched and removed by the isotropic dry etching process having a sufficiently large selective etching ratio with respect to SiO
2
and then the heat treatment for reducing the film stress of the buried oxide film
14
is effected at a temperature of 1000° C., for example. After this, the SiO
2
film
21
on the Si substrate
11
is removed by the etching process using NH
4
F and a new SiO
2
film (sacrificial oxide film)
26
is formed on the Si substrate
11
by the thermal oxidation process at a temperature of 800° C., for example. Then, boron (B) is implanted with, for example, the acceleration energy 200 keV and the dose amount of approx. 8×10
12
cm
−2
in order to form a p-well region
12
and boron (B) is further implanted in a condition that, for example, the acceleration energy is 50 keV and the dose amount is approx. 1×10
13
cm
−2
in order to control the threshold voltage of the n-channel MOSFET. Next, the heat treatment is effected at 1000° C. for 30 seconds to activate the doped impurity (FIGS.
6
A and
6
B).
Further, the sacrificial oxide film
26
on the surface of the Si substrate
11
is removed and the surface of the Si substrate
11
is thermally oxidized at a temperature of 750° C. to form a gate oxide film
15
with a thickness of 6 nm. Then, polycrystalline Si is deposited to 300 nm on the entire surface of the gate oxide film
15
by the LP-CVD method. A mask (resist pattern)
27
used for forming a gate electrode is formed by the photo-etching process and the polycrystalline Si film is patterned by the anisotropic dry etching process having a sufficiently large selective etching ratio with respect to SiO
2
with the resist pattern
27
used as a mask to form a gate electrode
16
(FIGS.
7
A and
7
B).
After this, arsenic (As) is ion-implanted into the Si substrate
11
in a condition that, for example, the acceleration energy is 50 keV and the dose amount is approx. 5×10
15
cm
−2
and the heat treatment is effected for approx. 30 seconds in an N
2
atmosphere of 1000° C. to form n
+
-type diffusion layers used as th
Banner & Witcoff , Ltd.
Chaudhuri Olik
Kabushiki Kaisha Toshiba
Louie Wai-Sing
LandOfFree
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