N-channel memory field effect transistor

Details N-channel memory field effect transistor N-channel memory field effect transistor

1977-09-19

1979-04-17

Wojciechowicz, Edward J.

357 13, 357 41, 357 45, 357 59, H01L 2978

Patent

active

041503899

ABSTRACT:
An erasible programmable read-only memory employing an n-chanel memory FET. A MOSFET is used having a floating memory gate which includes erasing projections ("tongues") on the floating memory gate. One tongue covers the drain and the other tongue covers the source. Erasing occurs bit-wise via the drain-side tongue; erasing word-wise or matrix-wise via the source-side tongue. Bit-wise, word-wise and matrix-wise erasing is obtained as desired. It is applicable for REPROM chips, and in particular, for programmable memories of miniature calculators.

REFERENCES:
patent: 3919711 (1975-11-01), Chou
patent: 3996657 (1976-12-01), Simko et al.
patent: 4004159 (1977-01-01), Rai et al.
patent: 4016588 (1977-04-01), Ohya et al.

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