N-channel clamp for ESD protection in self-aligned silicided CMO

Details N-channel clamp for ESD protection in self-aligned silicided CMO N-channel clamp for ESD protection in self-aligned silicided CMO

1990-04-27

1991-06-04

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 239, 357 42, 357 59, 307448, H01L 2906, H01L 2978, H01L 2702, H01L 2904

Patent

active

050218530

ABSTRACT:
An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors. A standard process for making CMOS integrated circuits having self-aligned silicided source/drain areas may be used, with the addition of only one non-critical masking step to block the siliciding of protection transistors.

REFERENCES:
patent: 4616243 (1986-10-01), Minato et al.
patent: 4760433 (1988-07-01), Young et al.
patent: 4825280 (1989-04-01), Chen et al.
patent: 4855620 (1989-08-01), Duvvury et al.
patent: 4907048 (1990-03-01), Huang
patent: 4949136 (1990-08-01), Jain

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