N-byte stack-oriented CPU using a byte-selecting control for enh

Details N-byte stack-oriented CPU using a byte-selecting control for enh N-byte stack-oriented CPU using a byte-selecting control for enh

1989-04-12

1993-01-12

Lee, Thomas C.

Boots, shoes, and leggings

395375, 364DIG1, 3642323, 3642393, 3642445, 3642475, 3642476, 3642477, 36426281, G06F 9455, G06F 930, G06F 300

Patent

active

051796910

ABSTRACT:
An apparatus for enhancing the operation of a M byte instruction word CPU when operating user programs on an N byte instruction word CPU. The M-Byte instruction word CPU is provided with an N-Byte instruction register and a main memory for supplying N-Byte instruction words or M-Byte instruction words to said N-Byte instruction register. An operational code multiplexer and an parameter code multiplexer are connectable to selective outputs of said instruction register so that any one of the M-Bytes may be selected as an operational code and any one of the remaining M-Bytes may be selected as parameter code bytes, and selection means including sequencer means are provided for operating the operational code multiplexer and the parameter code multiplexer in an M-Byte instruction word CPU mode of operation or as an N-Byte instruction word CPU mode of operation.

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