N-bit parallel input to variable-bit parallel output shift regis

Details N-bit parallel input to variable-bit parallel output shift regis N-bit parallel input to variable-bit parallel output shift regis

1991-12-16

1993-12-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701051, 375112, H04J 307

Patent

active

052727033

ABSTRACT:
N-parallel bits of data are input to a parallel in-parallel out shift register made of n+m n:1 parallel multiplexers and n-parallel bits of either pure data or combined stuff and data bits are output where, for cycles in which stuff bits are inserted, the non-outputted outputted data bits are recirculated for output on a subsequent cycle followed by newly incoming data bits; such is shown used to advantage in a bit stuffing technique where a synchronous payload envelope pattern may be started at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a selected point after the occurrence of the frame starting signal.

REFERENCES:
patent: 4301538 (1981-11-01), Desombre et al.
patent: 4928275 (1990-05-01), Moore et al.
patent: 5030951 (1991-07-01), Eda et al.
patent: 5033067 (1991-07-01), Cole et al.
patent: 5052025 (1991-09-01), Duff et al.
patent: 5067126 (1991-11-01), Moore

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