(N) bit (M) ternary coding circuit

Coded data generation or conversion – Digital code to digital code converters – To or from multi-level codes

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H03M 518

Patent

active

061149799

ABSTRACT:
A coding circuit of the present invention converts n-bit binary data word at a prescribed clock cycle (t) into to an m-trit ternary code word, where n and m are integers and n.gtoreq.m. The coding circuit includes an (x) number of storage elements or latches and a (y) number of coders, each storage element or latch receiving (m.div.x) bits of the binary data word at a clock cycle of (t.div.x). After a prescribed delay period, a corresponding storage element or latch outputs the sampled bits to a corresponding coder at an increasing or decreasing edge of the clock signal. Each coder codes the sampled bits to (m.div.y) ternary code. The each of the coders outputs (m.div.y) ternary code onto a corresponding signal line of a bus. Hence, the coding circuit outputs m-trit ternary code word onto the bus. An exemplary coding circuit is illustrated where n=8, m=6, t=25 MHz, x=2 and y=2, and D flip-flops are used for the storage elements and latches.

REFERENCES:
patent: 4805190 (1989-02-01), Jaffre et al.
patent: 5367535 (1994-11-01), Scholz
patent: 5525983 (1996-06-01), Patel et al.
patent: 5544323 (1996-08-01), Heaton et al.
"MAC Parameters, Physical Layer, Medium Attachment Units and Repeater for 100 Mb/s Operation;" Supplement to ANSI/IEEE Std. 802.3, 1993 Edition, Document #802.3u/D5.3.

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