N-bit carry select adder circuit with double carry select genera

Details N-bit carry select adder circuit with double carry select genera N-bit carry select adder circuit with double carry select genera

1986-03-03

1988-08-16

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

047648880

ABSTRACT:
A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to initially provide two sum bits and two output carry bits for each bit position corresponding to carry input bits of zero and one, respectively. The section adders comprise full adders and are divided into at least two ranked groups in which sum bits are concurrently calculated in each group. Each full adder concurrently provides two sum bits for each rank ordered output sum bit. The rank ordered carry select logic circuits sequentially provide carry select bits which are used by the full adders to select one of the two sum bits as the output sum bit. Two output carry bits are concurrently provided by each group. One of the two output carry bits of the lowest ranked group is provided as a half carry output bit in response to the carry input bit. One of the two output carry bits of the highest ranked group is provided as the sum output carry bit in response to the half carry bit of the lower ranked group.

REFERENCES:
patent: 3100835 (1963-08-01), Bedrij
patent: 3993891 (1976-11-01), Beck et al.
patent: 4525797 (1985-06-01), Holden
patent: 4573137 (1986-02-01), Ohhashi
patent: 4675837 (1987-06-01), Ulbrich et al.
patent: 4675838 (1987-06-01), Mazin et al.
patent: 4682303 (1987-07-01), Uya
IBM Tech Disclosure Bulletin, vol. 28 No. 1, Jun. 1985, pp. 68-70, "Modified ones complement carry-completion-sensing adder".
Schmookler, "Design of Large ALUs Using Multiple PLA Macros", IBM J. Res. Develop. vol. 24, No. 1, Jan. 1980, pp. 2-14.

Affiliated with

Also associated with

Rating

N-bit carry select adder circuit with double carry select genera does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with N-bit carry select adder circuit with double carry select genera, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and N-bit carry select adder circuit with double carry select genera will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-604347