N-bit carry select adder circuit having only one full adder per

Details N-bit carry select adder circuit having only one full adder per N-bit carry select adder circuit having only one full adder per

1983-01-03

1985-06-25

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

045257973

ABSTRACT:
An n-bit adder circuit, where n is an integer, for providing carry select addition of two input numbers is provided. A rank ordered plurality of section adders each have a plurality of full adders. Each full adder utilizes a single half adder to provide two sum bits which are coupled to a multiplexer which is an integral part of each section adder. One sum is for a carry-in and the other sum is for no carry-in. A method of minimizing logic circuitry which provides carry bits and carry sum select bits is provided. The carry bits and carry sum select bits control which of the two sums are provided by each section adder. By providing the carry bits and carry sum select bits in complement form every other order of section adder, logic circuitry and logic gate delays are minimized.

REFERENCES:
patent: 3100835 (1963-08-01), Bedrij
patent: 3316393 (1967-04-01), Ruthazer
patent: 3553446 (1971-01-01), Kruy
patent: 3638003 (1972-01-01), Meixner
patent: 3993891 (1976-11-01), Beck et al.
Bedrij, "Carry-Select Adder," IRE Trans. on Electronic Computers, Jun. 1962, pp. 340-346.

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