N+0.5 wait state programmable DRAM controller

Details N+0.5 wait state programmable DRAM controller N+0.5 wait state programmable DRAM controller

1991-02-27

1997-06-03

Swann, Tod R.

395878, G06F 1316

Patent

active

056363672

ABSTRACT:
CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N+0.5 processor wait states. The half wait state average is obtained by forcing the system CPU to measure wait states in processor clock time units which are twice the period of an independent clock in the DRAM controller which, in turn, triggers RAS and CAS assert and de-assert. RAS or CAS is thus able to assert 1/2 processor clock period earlier in one memory cycle relative to the last. Early assert time also provides for an early de-assert time so that data can be transferred to/from the DRAM more quickly than previously possible.

REFERENCES:
patent: 4575794 (1986-03-01), Veneski et al.
patent: 4797850 (1989-01-01), Amitai
patent: 5032982 (1991-07-01), Dalrymple et al.
patent: 5033027 (1991-07-01), Amin
patent: 5047924 (1991-09-01), Fujioka et al.
patent: 5077686 (1991-12-01), Rubenstein
patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5097437 (1992-03-01), Larson
patent: 5167031 (1992-11-01), Watanabe
patent: 5179713 (1993-01-01), Catlin et al.

Affiliated with

Also associated with

Rating

N+0.5 wait state programmable DRAM controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with N+0.5 wait state programmable DRAM controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and N+0.5 wait state programmable DRAM controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-399411