Mutual-interpolating delay-locked loop for high-frequency...

Details Mutual-interpolating delay-locked loop for high-frequency... Mutual-interpolating delay-locked loop for high-frequency...

2006-08-08

2008-01-29

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

07323918

ABSTRACT:
A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.

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Sun et al. “A 1.25GHz 0.35-μm Monolithic CMOS PLL Based on a Multiphase Ring Oscillator,” IEEE Journal of Solid-State Circuits, vol. 36, No. 6, Jun. 2001, pp. 910-916.

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