Mutual charge cancelling sample-reset loop filter for phase...

Details Mutual charge cancelling sample-reset loop filter for phase... Mutual charge cancelling sample-reset loop filter for phase...

2008-03-28

2009-11-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000, C327S558000

Reexamination Certificate

active

07619452

ABSTRACT:
In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle.

REFERENCES:
patent: 7142037 (2006-11-01), Josefsson
patent: 7450041 (2008-11-01), Lin et al.
Maneatis, John G., “FA 8.1: Low-Jitter and Process-Independent DLL and PLL Based on Self Biased Techniques”,1996 IEEE International Solid-State Conference, (1996), 3 pages.
Maneatis, John G., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL”,IEEE Journal of SOlid-State Circuits, vol. 38, No. 11, (Nov. 2003), pp. 1795-1803.

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