Multizone array processor implementing two sided zone buffers wi

Details Multizone array processor implementing two sided zone buffers wi Multizone array processor implementing two sided zone buffers wi

1985-10-04

1989-08-22

Zache, Raulfe B.

Boots, shoes, and leggings

364736, 364704, G06F 1500, G06F 1516, G06F 1531, G06F 1300

Patent

active

048602493

ABSTRACT:
A reconfigurable processor array (RPA) for performing high speed operations on data arrays and eliminating I/O bottleneck. The array memory has a working side for storing arrays to be processed during a given array operation, and an I/O side for loading an array to be used during a subsequent operation and downloading an array resulting from a preceding operation.

REFERENCES:
patent: 3787673 (1974-01-01), Watson et al.
patent: 3875391 (1975-04-01), Shapiro et al.
patent: 4075688 (1978-02-01), Lynch, Jr. et al.
patent: 4541048 (1985-09-01), Propster et al.
patent: 4546428 (1985-10-01), Morton
patent: 4580215 (1986-04-01), Morton
patent: 4589067 (1986-05-01), Porter et al.

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