Multivalued multiplier for binary and multivalued logic data

Details Multivalued multiplier for binary and multivalued logic data Multivalued multiplier for binary and multivalued logic data

1993-09-13

1995-08-01

Mai, Tan V.

Boots, shoes, and leggings

364754, G06F 700, G06F 752

Patent

active

054385334

ABSTRACT:
A multivalued multiplier is arranged to treat a plurality of multivalued signals at one time without having to increase the circuit scale. The multivalued multiplier includes a logic circuit and a multivalued circuit connected to the logic circuit. The logic circuit serves to receive two or more signals and output a predetermined logic result. The multivalued circuit serves to process the predetermined logic result and output a predetermined multivalued signal.

REFERENCES:
patent: 4914614 (1990-04-01), Yamakawa
patent: 5227993 (1993-07-01), Yamakawa
patent: 5289399 (1994-02-01), Yoshida
patent: 5299145 (1994-03-01), Yoshida

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