Multivalued adder having capability of sharing plural multivalue

Details Multivalued adder having capability of sharing plural multivalue Multivalued adder having capability of sharing plural multivalue

1993-11-23

1995-11-14

Mai, Tan V.

Boots, shoes, and leggings

364768, G06F 700

Patent

active

054672988

ABSTRACT:
A multivalued adder for processing addition of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input circuit includes parallel inputs for binary logic and multivalued logic, and receives the first data. The first input circuit also outputs a first set of bit data representing the first data. Similarly, the second input circuit includes parallel inputs for binary logic and multivalued logic, and receives the second data. The second input circuit also outputs a second set of bit data representing the second data. An adding circuit, connected to the first and said second input circuits, adds the second set of bit data and the first set of bit data. An output circuit, connected to the adding circuit, converts the output of the adding circuit into data in binary logic and multivalued logic, in parallel, and outputs converted data in binary logic and multivalued logic, in parallel.

REFERENCES:
patent: 4914614 (1990-04-01), Yamakawa
patent: 5227993 (1993-07-01), Yamakawa
patent: 5299145 (1994-03-01), Yoshida

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