Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
Reexamination Certificate
2005-04-01
2011-12-06
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Vector processor
Reexamination Certificate
active
08074051
ABSTRACT:
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
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Glossner C. John
Hokenek Erdem
Moudgill Mayan
Schulte Michael J.
Aspen Acquisition Corporation
Knobbe Martens Olson & Bear LLP
Petranek Jacob
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