Multiplex communications – Pathfinding or routing – Store and forward
Reexamination Certificate
1998-08-03
2002-10-15
Patel, Ajit (Department: 2664)
Multiplex communications
Pathfinding or routing
Store and forward
C711S153000
Reexamination Certificate
active
06466581
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to data transfer systems and more particularly to data transfer systems involving transfer of data over a common bus from a processor that stores data in fragmented memory location to another processing unit wherein the data transferred may be multistream data.
Personal computers, work stations and other computers are increasingly incorporating more and more multimedia functions, such as digital video disc players, CD players, TV tuners, modems, and other multimedia components. As a result, computer users can mix digital audio from one audio source such as a DVD player and another audio source such as a CD ROM game. In addition, computer users may be able to receive video or audio information through a modem connection over the Internet while simultaneously playing a movie or mixing audio from other audio sources. The output rate to the audio speakers typically dictates the rate at which data needs to be supplied from the host. In other words, if DVD audio is transmitted at a given rate, real time processing of the audio may require a 48 kilohertz sampling rate of output to speakers connected the multimedia computer system. Multistream audio may need to be processed in real time and output to speakers or other software applications in the system such as when movies are being played.
With some host buses, such as the Intel® PCI bus, a host application typically allocates buffer fragments in system memory to be used in a bus mastering operation. Data is written into these buffers by the host application. The host bus master control program creates a bus master list descriptor table. This descriptor table typically contains an array of bus master list descriptor entries. Each of these entries contains the base address of a buffer, the buffer's size and flags to indicate the end of the circular buffer or the end of the list. In some systems, the host memory can have as many as thirty-two descriptors—one for each stream. The data in the descriptor table also indicates whether the stream must be read or whether it is being written.
A problem arises in such multimedia systems when the same bus is required to transfer data from two sources or two destinations, particularly when some of the data must be processed in real time. Moreover, combining an audio mixing processor on the same chip or circuit board as a digital signal processor for modem processing, can be very expensive if the system utilizes separate bus interfaces for each stream of information. For example, multimedia systems can have sixteen, thirty-two or more audio stream sources connected to a host PC. If some of the audio sources operate at different sampling rates and require real time audio processing, individual bus interfaces between the audio and modem system in the host PC would result in a highly complex and highly costly audio and modem system. For example, where a host processor receives multistreams of audio data from multiple sources such as a DVD and a stored audio file or television tuner, this multistream audio typically has to be processed in real time particularly where for example the audio from the T.V. tuner generating a broadcast of live coverage. Where other processes are also being performed simultaneously, such as modem communication using the host processor, a separate modem processing chip may be incorporated in addition to an audio processing chip wherein both the audio processing chip and the modem processing chip share the common bus to the host processor.
A conventional system may typically only allow either the audio processing chip or modem processing chip to access the bus at a given time, at a fixed rate. Where audio processing is required for example, a digital signal processor may operate at high clock speeds on the order of 100 MHz and may require large bandwidths of throughput to maintain a specified sampling rate for output data to facilitate real time output to speakers or to other further processing blocks. Moreover, the rate at which such a DSP would require data depends upon the type of applications that are in operation. Hence the data throughput demand differs depending upon the applications running on the DSP. Proposed multimedia systems include provision for up to as many as 32 concurrent streams of audio where the streams may be supplied at different sampling rates. In addition, some streams are compressed and require the decompression prior to processing.
A conventional technique for accommodating the varying sampling rates is to provide large buffer memories that are accessible by each of the multiple digital signal processors. However, memory can be prohibitively expensive particularly where high quality and low cost solutions are desired. In addition, it is desirable to avoid frequent interrupts of the host processor to minimize performance degradation particularly when large numbers of multistreams of data must be processed.
Another conventional technique for transferring data from one processor to multiple processors includes the use of a synchronized arbitor that arbitrates between multiple processors on a synchronized basis. However, such systems can become bottlenecks particularly in systems employing multistream data, since real time processing may be desired by one processor but the arbitor may be synchronized to give priority to another processor. Hence such systems may be inflexible in accommodating varying load demands presented by multimedia systems. In addition, such systems typically utilize dual ported memory such that both a primary or host processor and another processor can access the same memory. Such dual ported memory configurations can increase the cost of the system.
Other known techniques for transferring data from a host processor to a plurality of other processors on the same bus include treating the peripheral processors as slaves such that numerous interrupts must be sent to the host processor to notify the host processor to transfer or receive data from the slave digital signal processors. Such a configuration can unnecessarily slow down the operation of the overall system by introducing unnecessary interrupts particularly where real time multistream data is being transferred over the bus.
Consequently there exists a need for a host interface control system for transferring data over a host bus when a host processor shares a bus with a plurality of other digital signal processors, such as those that may process the data in real time.
REFERENCES:
patent: 5283781 (1994-02-01), Buda et al.
patent: 5650825 (1997-07-01), Naimpally et al.
patent: 5675642 (1997-10-01), Sone
patent: 6009108 (1999-12-01), Takehara et al.
patent: 6127953 (2000-10-01), Manzardo
Giemborek Vladimir F.
Yee James C.
ATI Technologies Inc.
Patel Ajit
Vedder Price Kaufman & Kammholz
LandOfFree
Multistream data packet transfer apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multistream data packet transfer apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistream data packet transfer apparatus and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2987041