Multistepped threshold convergence for a flash memory array

Details Multistepped threshold convergence for a flash memory array Multistepped threshold convergence for a flash memory array

1994-07-01

1996-11-19

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 3651853, G11C 1140

Patent

active

055769918

ABSTRACT:
A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.

REFERENCES:
patent: 5122985 (1992-06-01), Santin
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5295107 (1994-03-01), Okazawa et al.
patent: 5327385 (1994-07-01), Oyama
patent: 5357476 (1994-10-01), Kuo et al.
J. Chen, N. Radjy, S. Cagnina and J. Lien, "Study of Over Erase Correction Convergence Point Vth*," Advanced Micro Devices Technology Conference, 1994, pp. 68-69.
S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke and M. Wada, "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM," IEEE Tech. Dig. IEDM 1991, pp. 307-310.

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