Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Patent
1992-07-02
1994-02-15
Logan, Sharon D.
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
341145, 341172, 341141, 341118, H03M 114, H03M 142
Patent
active
052871088
ABSTRACT:
An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value. A set of successive comparison voltages are generated in the third conversion cycle by selectively switching combinations of reference voltages with binary weighted capacitors. The resulting comparison voltages are stepped in 1 LSB increments, which is one fourth the voltage increment between neighboring reference voltages produced by the resistance ladder circuit, and cover a predefined range of voltages above and below the voltage associated with the ten-bit value generated during the first two conversion cycles. Then a voltage derived from the input voltage is compared with these generated voltages to generate a correction value that is combined with the ten-bit value generated during the initial conversion cycles to produce a 12-bit conversion value.
REFERENCES:
patent: 4896155 (1990-01-01), Craiglow
patent: 4918449 (1990-04-01), Chin
patent: 5057841 (1991-10-01), Veerhoek et al.
patent: 5138319 (1992-07-01), Tesch
"A Multistep A/D Converter Family with Efficient Architecture"; Michael K. Mayes and Sing W. Chin; IEEE Log No. 8931436; IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989.
Chin Sing W.
Mayes Michael K.
Logan Sharon D.
National Semiconductor Corporation
LandOfFree
Multistep analog-to-digital converter with successive approximat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multistep analog-to-digital converter with successive approximat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistep analog-to-digital converter with successive approximat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1210559