Coded data generation or conversion – Converter calibration or testing – Trimming control circuits
Patent
1992-07-02
1993-06-08
Logan, Sharon D.
Coded data generation or conversion
Converter calibration or testing
Trimming control circuits
341118, 341156, 341120, H03M 106, H03M 114
Patent
active
052183629
ABSTRACT:
An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value. In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.
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"A Multistep A/D Converter Family with Efficient Architecture"; Michael K. Mayes and Sing W. Chin; IEEE Log No. 8931436; IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989.
Chin Sing W.
Mayes Michael K.
Logan Sharon D.
National Semiconductor Corporation
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