Multistate microprocessor bus arbitration signals

Details Multistate microprocessor bus arbitration signals Multistate microprocessor bus arbitration signals

1993-06-21

1995-12-12

Geckil, Mehmet

Boots, shoes, and leggings

395293, 395729, 395800, 364DIG1, 3642426, 36424292, 3642405, 3642434, G06F 1314

Patent

active

054758505

ABSTRACT:
A microprocessor bus arbitration communications scheme for enhancing efficiency and performance of a multi-master bus system, typically within a computer system, including a central processing unit ("CPU") being a primary bus master, a bus arbiter and at least one alternative bus master coupled together by a bus. The CPU includes an internal memory element, a bus queue and bus control logic which collectively operate to generate a plurality of microprocessor bus arbitration signals to the bus arbiter. These microprocessor bus arbitration signals include a first bus arbitration signal indicating whether the CPU requires access to the bus and a second bus arbitration signal indicating that the CPU requires immediate access to the bus.

REFERENCES:
patent: 5146596 (1992-09-01), Whittaker et al.
patent: 5157774 (1992-10-01), Culley
patent: 5168568 (1992-12-01), Thayer et al.
patent: 5287477 (1994-02-01), Johnson et al.

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