Multistaged frequency conversion with single local oscillator

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

Reexamination Certificate

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Details

C455S314000, C455S318000, C455S323000, C455S255000

Reexamination Certificate

active

06282413

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a frequency-conversion circuit comprising a multistage frequency-converting means and an oscillator output coupled to at least one oscillator input of the multistage frequency-converting means.
The present invention also relates to a telecommunication system, a receiver, a transmitter, a transceiver, an integrated circuit, and a telephone device provided with such a frequency-conversion circuit.
Such a frequency-conversion circuit is known from “High Integration CMOS RF Transceivers”, Proc. of the Workshop on Advances in Analog Circuit Design, Apr. 2-3-4, 1996, Lausanne-Ouchy, Switzerland, by F. Brianti et al., 14 pages. This article describes in particular integrated digital radio architectures having a frequency up or down converting means usable, for example, in low-IF, such as zero-IF, or wideband-IF configurations. By definition, a low-IF configuration, such as a receiver, transmitter or transceiver, is a configuration, wherein the intermediate frequency (IF) is close to zero, or zero in the case of zero-IF. Some known advantages of zero-IF configurations are the high degree of integration on a chip that can be achieved as compared to a heterodyne or conventional IF configuration, because of the possibility to apply filters, such as low-pass filters for channel selectivity, that can be integrated at low cost. Reduced power dissipation, fewer interference problems and better crosstalk control than in a conventional configuration that requires external components can be achieved with a careful design using this zero-IF architecture. The frequency conversion is implemented by means of two stages of mixers (see
FIG. 2
) resulting in a multistage frequency conversion in order to reduce the requirements imposed upon image rejection filters in front of the mixers as compared to conventional architectures. The mixer stages are quadrature mixer stages each having an I-path and a Q-path in order to properly distinguish between positive and negative frequencies, corresponding to upper and lower sidebands of an input RF signal. These quadrature mixers eliminate an off-chip IF filter function. Each of the two stages is being fed by a separate voltage-controlled oscillator (VCO) phase-locked loop (PLL) synthesizer circuit. Both synthesizer circuits are connected to a common crystal oscillator. The problem of the known frequency conversion circuit is that two synthesizer circuits are needed, which circuits lead to significant costs and require a large surface, area and much power.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the chip area and power consumption needed for integrated architectures. To achieve this, the frequency-conversion circuit according to the invention is characterised in that the frequency-conversion circuit comprises a frequency-divider means coupled between the oscillator output and at least one further oscillator input of the multistage frequency-converting means. The frequency-conversion circuit according to the invention has the advantage that one VCO/PLL circuit can be dispensed with, thus saving components, cost and chip area, and reducing power dissipation and weight, which is particularly important in mobile communication applications of the frequency-conversion circuit, such as telephone systems. In addition, integration of only one of such VCO/PLL circuit is more easy and only involves a minimum number of components.
In an embodiment of the frequency-conversion circuit according to the invention, the frequency divider means comprises a counter means. Such counter means are very simple to integrate. Furthermore, the counter means provide for an exact relation as a function of time, in particular the phase, between the respective oscillator signals intended for each stage of the multistage frequency-converting means. Because of the inherent phase accuracy between the respective oscillator signals derived from both respective outputs of the counter means, a good image or mirror signal suppression is automatically achieved so that, if necessary at all, a modest image rejection-suppression filter will be sufficient in practise to reveal a high-quality frequency conversion. In general, the counter means already have or can easily be provided with outputs for providing both the I and Q oscillator signals to be applied to the I and Q paths respectively, of the multistage frequency-converting means. So separate 90° phase shifters are no longer necessary in the coupling or direct connection between the generally local oscillator and, in particular, the Q paths' oscillator inputs of the multistage frequency-converting means.


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“High Integration CMOS RF Transceivers”, Proc. of the Workshop on Advances in Analog Circuit Design, Apr. 2-3-4, 1996, Lausanne-Ouchy, Switzerland, by F. Brianti et al, 14 pages.

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