Multistage precision, low input/output overhead, low power,...

Details Multistage precision, low input/output overhead, low power,... Multistage precision, low input/output overhead, low power,...

2001-07-09

2003-01-14

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C323S315000

Reexamination Certificate

active

06507236

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to electronic circuits, and is particularly directed to new and improved multistage current mirror circuit architecture, that is configured to minimize transistor base current errors or offsets in a low voltage application such as, but not limited to, the coupling to a low voltage codec of a subscriber line interface circuit, having very high output impedance and minimum crosstalk.
BACKGROUND OF THE INVENTION
System equipments of telecommunication service providers customarily contain what are known as subscriber line interface circuits or ‘SLICs’, to interface communication signals with the tip and ring leads of a wireline pair used to serve a relatively remote piece of subscriber communication equipment. In order that they may be interfaced with a variety of telecommunication circuits, including those providing codec functionality, present day SLICs must conform with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low noise, low power consumption, filtering, and ease of impedance matching programmability.
Through the use of differential voltage-based implementations, designers of integrated circuits used for digital communications, such as codecs and the like, are able to lower voltage supply rail requirements for their devices (e.g., from a power supply voltage of five volts down to three volts). As a result, the communication service provider now faces the problem that such low voltage restrictions may not provide sufficient voltage headroom to accommodate a low impedance-interface with existing SLICs (such as those designed to operate at a VCC supply rail of five volts).
This limited voltage headroom problem may be illustrated by considering the design and operation of a conventional current mirror architecture, such as that shown in
FIG. 1
, which is of the type employed in a subscriber line interface circuit, and operates with a customary VCC supply rail of five volts. In this conventional current mirror design, an input NPN transistor
10
has its base
11
coupled to a voltage reference V
REF
, and its emitter
12
coupled to receive an emitter current I
12
or input current I
in
, from a digital communication device, such as a codec.
The collector
13
of the input NPN transistor
10
is coupled in common to the collector
23
of a first current mirror input PNP transistor
20
, and to the base
31
of a base current compensator PNP transistor
30
; the collector
33
of which is coupled to a voltage reference terminal, such as ground (GND). The emitter
32
of the base current compensator PNP transistor
30
is coupled in common to the base
21
of the current mirror input transistor
20
and to the base
41
of a PNP current mirror output transistor
40
. The emitters
22
and
42
of current mirror transistors
20
and
40
are respectively coupled through resistors
24
and
44
to a (VCC) voltage supply rail
16
, while the collector
43
of the current mirror output transistor
40
is coupled to an output terminal
45
, from which an output current IOut is derived.
Although working reasonably well when operating at a designed power supply rail voltage VCC of five volts, the current mirror of
FIG. 1
lacks sufficient overhead for proper circuit operation, when interfaced with a circuit (such as a differential voltage-based codec) that operates at a much lower VCC rail value (e.g., on the order of only three volts and a reference voltage V
REF
of only half that value). In addition, although the mirrored output current I
out
at the output node is first order compensated for PNP base current errors, it is not compensated for the NPN base current error in the input transistor.
More particularly, the mirrored output current I
out
at the current mirror's output terminal
45
corresponds to the collector current I
43
flowing out of the collector
43
of the current mirror output transistor
40
which, for equal geometry current mirror input and output transistors, may be defined as:
I
out
=I
43
=&agr;
NPN10
I
12
−2
I
12
/&bgr;
PNP
2
,
or
I
out
=I
12
(&agr;
NPN10
−2/&bgr;
PNP
2
).
Therefore, the value of the mirrored output current I
out
may be approximated as:
I
out
=I
in
(1−1/&bgr;
NPN
).  (1)
From equation (1), it can be seen that the mirrored output current I
out
at the collector
43
of the current mirror output transistor
40
not only includes the desired input current I
in
, but contains an undesired base current error component I
in
/&bgr;
NPN
associated with the NPN input transistor
10
.
Due to the extremely tight voltage tolerances associated with the use of substantially lower VCC supply rail and reference V
REF
voltages, there is no available headroom in the collector-emitter current flow path through transistors
10
-
20
and the VCC supply rail for insertion of an NPN base current error compensating transistor.
As an alternative architecture, the input transistor
10
may be removed, with the input current I
in
applied directly to the collector
23
of the current mirror input transistor
20
. However, this does not resolve the base current error problem, since the overhead voltage at the circuit's input port (the collector
23
of current mirror input transistor
20
) is again two base-emitter diode voltage drops (Vbe
20
+Vbe
30
) below VCC.
For this alternative circuit implementation, the mirrored output current may be defined as:
I
out
=I
in
(1−1/&bgr;
P
2
).  (2)
In accordance with the invention described in the '439 application, this base current error problem is successfully remedied by the current mirror circuit architecture shown in FIG.
2
. This improved current mirror provides an overhead voltage that substantially reduces base current error, and offers a one base-emitter diode drop improvement over the overhead voltage of the conventional circuit. To this end, a bipolar PNP input current mirror transistor
50
of a current mirror input stage
200
has its base
51
coupled to the base
61
of a first bipolar PNP output current mirror transistor
60
of a first current mirror output stage
210
-
1
and to the base
71
of a second bipolar NPN output current mirror transistor
70
of a second current mirror output stage
210
-
2
.
The respective emitters
52
,
62
and
72
of the current mirror transistors
50
,
60
and
70
are coupled (either directly of through resistors) to the power supply rail VCC. The first current mirror output transistor
60
of the first output stage
210
-
1
has its collector
63
coupled to a first current output port Iout_
1
, while the second current mirror output transistor
70
of the second output stage
210
-
2
has its collector
73
coupled to a second current output port Iout_
2
. The out put currents produced at the output currents I
out
—
1
and I
out
—
2
of respective output stages
210
-
1
and
210
-
2
are proportional to the geometry ratios of the output transistors
60
and
70
to the current mirror input transistor
50
.
As in the conventional current mirror architecture of
FIG. 1
, the base
51
of the current mirror input transistor
50
is coupled to the emitter
82
of a base current compensator PNP transistor
80
. However, rather than having its base
81
connected directly to the collector
53
of the current mirror input transistor
50
, the base current compensator transistor
80
has its base coupled to the emitter
92
of an NPN base current error-reduction transistor
90
. The NPN base current error-reduction transistor
90
and the base current compensator PNP transistor
80
form a buffer circuit between the current mirror and an input terminal Iin, to which the input current I
in
is coupled.
The base current error-reduction NPN transistor
90
has its base
91
coupled to the collector
53
of transistor
50
of the current mirror input stage
200
, and its collector
93
is coupled to the VCC supply rail. The emitter
92
of transisto

Affiliated with

Also associated with

Rating

Multistage precision, low input/output overhead, low power,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multistage precision, low input/output overhead, low power,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistage precision, low input/output overhead, low power,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3017032