Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-11-21
2002-10-15
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S144000
Reexamination Certificate
active
06466066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multistage pipeline latch circuit advantageously used in LSI design, and relates in particular to a latch circuit that take into account the timing of the data input and the clock input and a multistage pipeline latch circuit and manufacturing method for the same.
2. Description of the Related Art
Conventionally, in order to form a multistage pipeline latch circuit during LSI design, generally, flip-flop circuits, latch circuits, and the like are used. Here, a pipeline latch circuit denotes a circuit that transmits stored data in sequence using flip-flop circuits, latch circuits, and the like.
FIG. 8
is a structural drawing of the packaged state of a two stage pipeline latch circuit formed using flip-flop circuits and latch circuits, and shows the reference clock CLK, the flip-flop FF package, the latch packages (A) to (C), and the latch insertion positions. The reference clock CLK has a clock frequency that can carry at least two clock wavelengths, one at a start point flip-flop
000
and one at an end point flip-flop
002
. When the clock frequency is 100 MHz, for example, one cycle of the clock becomes 10 nsec, which cannot be ignored even when compared to the switching speed of a switching transistor, and thus the clock waveform distribution will appear in the wiring pattern that connects the flip-flop circuits and the latch circuits.
The start point flip flop
000
, middle flip flop
001
, and the end point flip flop
002
are rising edge flip-flops FF. The latch circuit
003
is an LL latch circuit with a through period when the clock is 0 (low) and a hold period when the clock is 1 (high). The latch circuit
004
is an LH latch circuit with a through period when the clock is 1 and a hold period when the clock is 0. Reference numerals
010
to
014
denote logic gates. The clock waveform
020
is the clock waveform CKL input to the flip flop circuits FF and the latch circuits LL and LH.
As shown by the FF package in
FIG. 8
, in the case of packaging a two stage pipeline using flip flop circuits, the delay of the logic gates between flip flop circuits must fulfill the following Equations. Here, the waveform of the clock is assumed to be ideal. (conditions for the insertion position of the middle flip flop
001
)
Ftpd+D
010
+
Fset≦Tclk
(1)
Ftpd+D
011
+
Fset≦Tclk
(2)
Here, Ftpd and Fset respectively denote the delay time and the setup time of the flip flop circuit, D
010
and D
011
respectively denote the delay times of logic gate
010
and
011
, and Tclk denotes the clock cycle. Using Equations 1 and 2, the logic gates having a maximum delay time of Tclk−Ftpd−Fset can be incorporated between flip flop circuits.
The maximum delay of the logic gates permitted during 2 clock cycles becomes:
D
0
10
+
D
011
=2(
Tclk−Ftpd−Fset
) (3)
There is only one point for the insertion position of the flip flop
001
in order to incorporate logic gates having the delay in Equation 3, and when displaced from this point, the maximum delay of the logic gates (
3
) must be decreased to less than Equation 3. In the design of flip flop circuits, there is a wait from the input of the data into the flip flop circuit until the rise of the clock, and when this waiting time increases, the maximum delay of the logic gates (
3
) is reduced.
Next, as shown in
FIG. 8
, in the case of packaging the two stage pipeline using flip flop circuits and latch circuits, data input into the latch circuits is fixed during the through period. When carried out using this structure, the waiting for the clock that occurs at the middle flip flop circuit package does not occur at the latch circuits. The maximum delay time permitted in two clock cycles becomes:
D
012
+
D
013
+
D
014
=2
Tclk−
2
Ldel−Ftpd−Fset
(4)
Here, Ldel denotes the through delay time of the latch circuit, and D
012
, D
013
and D
014
respectively denote the delay times of the logic gates
012
,
013
, and
014
. The insertion positions of latch circuits
003
and
004
for incorporating logic gates having the delay of Equation 4 have a permitted width, and the data input to the latch circuits can be defined during the through period.
The conditions for the insertion positions of the latch circuits become the following:
(conditions for the insertion position of latch circuit
003
)
Ftpd+D
012
+
Lset<Tclk
(5)
Ftpd+D
012
≧1/2·
Tclk
(6)
(conditions for the insertion position of latch circuit
004
)
Ftpd+D
012
+
Ldel+D
013
+
Lset≦
3/2·
Tclk
(7)
Ftpd+D
012
+
Ldel+D
013
≧
Tclk
(8)
Equations 5 and 6 are the conditions for the insertion position of latch circuit
003
, and Equations 7 and 8 are the conditions for the insertion position of latch circuit
004
. Therefore, the latch circuit packages A to C in
FIG. 8
represent the packaging at the limits satisfying these conditions, the insertion positions of the latch circuits have a permitted width, and the conditions are not as severe as the case of using flip flop circuits. To the extent that these conditions in Equations 5 to 8 are satisfied, the maximum delay of the logic gates can be maintained at the value in Equation 4.
However, in the design of latch circuits, depending on the insertion positions of the latch circuits, the circuits may not be able to tolerate any displacement of the clock edge, and thus if the clock edge is only slightly displaced, an operational error can occur. The displacement of the clock edge occurs due to skew caused by variations in performance of the transistors during the LSI production process and jitter during LSI operations, for example. In addition, the percentage of skew and jitter with respect to the clock cycle becomes large as the operating frequency of LSI increases, and thus forming a circuit that can tolerate displacement of the clock edge is indispensable.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a multistage pipeline latch circuit and a manufacturing method for the same that tolerates displacement of the clock edge by utilizing the insertion positions for the latch circuits and timing of the clock input into the latch circuits.
The multistage pipeline latch circuit according to a first aspect of the invention for resolving the above-described problems, provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, wherein this latch circuit, which operates as a two or more stage pipeline, provides a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuits, and a circuit insertion position selection means that determines the insertion position of the input and output flip flop circuits and the latch circuits such that the input of the latch circuit is defined at the center of the through period of the latch circuit.
In an apparatus constructed in this manner, the insertion position of the input and output flip flop circuit and the latch circuit is determined by the circuit insertion position selection means so that the input of the latch circuit is defined at the center of the through period of the latch circuit, and thus the operation of LSI manufacture is stabilized so that the influence received by the multistage pipeline latch circuit from the Skew due to the variation in the transistor performance, the jitter, and duty ratio that occur during operation of the LSI, etc., is minimized.
Preferably, in a second aspect of the invention, the latch circuit has an LL latch circuit and an LH latch circuit, and the circuit insertion position determination means is structured having as a condition for the LL latch that:
Ftpd+D
110
=3/4·
Tclk−
1/2·
Lse
Lam Tuan T.
NEC Corporation
Scully Scott Murphy & Presser
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