Multistage pipeline bit conversion

Multiplex communications – Communication techniques for information carried in plural... – Adaptive

Reexamination Certificate

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C710S066000, C341S067000

Reexamination Certificate

active

07006527

ABSTRACT:
A system and method that converts a series of input data words at a first data width to a series of output data words at a smaller data width. In order to achieve 10-Gigabit Ethernet over an optical network, data must be converted from 66-bit words to 64-bit words (the smaller data width) at a faster clock rate, such that the concatenation of the series of input data is equivalent to the concatenation of the series of output data. This is accomplished by shifting the input data such that it is either prefixed by zeros, suffixed by zeros, or both, depending on the stage of the progression of the series. The shifted data is then split up, with a portion of the data going into a delay register and another portion of the data either being output directly or combined with data previously stored in the delay register.

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patent: 6429794 (2002-08-01), Widmer et al.
patent: 6598103 (2003-07-01), MacWilliams et al.
patent: 6633944 (2003-10-01), Holm et al.
patent: 6892252 (2005-05-01), Tate
10 Gigabit Ethernet Alliance [online]. “10 Gigabit Ethernet Technology Overview White Paper”, May, 2001 Revision 1.0. Retrieved from Internet: <URL: http://www.10gea.org>.
Agere Systems, “10 Gigabit Ethernet PCS Intellectual Property Cores (Preliminary Data Sheet)”, Jul. 2001. Retrieved from <URL: www.agere.com>.
Dugan, et al., “64b/66b Coding Update” [Presentation Materials], IEEE 802.3ae, Albuquerque, NM, Mar. 6, 2000.
McCarley [Initiator of discussion], ‘Re: 64b/66b gearbox in FPGA.’ (Threaded Discussion on the Comp.arch.fpga vsnet newsgroup) [online], Jan./Feb., 2001. Retrieved from Internet:<URL: www.fpga-faq.com/archives/28975.html> and similar pages [retrieved on Jun. 22, 2001].

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