Multistage offset-cancelled voltage comparator

Details Multistage offset-cancelled voltage comparator Multistage offset-cancelled voltage comparator

1990-10-04

1991-11-12

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307362, 307494, H03K 522, H03K 5153, G06G 712

Patent

active

050650459

ABSTRACT:
A multistage voltage comparator having plural transfer stages between successive comparator stages. Each transfer stage includes capacitors connected between the outputs of one stage and the inputs of the next stage. The capacitors are also connected to a reference voltage line via MOS transistor switches. The switches are characterized by progressively slower turn-off times for each successive transfer stage so that turn off is sequential. The comparator is a differential amplifier with two complementary inputs and outputs. The complementary outputs of the final stage are loaded into a latch and then transferred to an RS flip-flop providing a digital logic output representative of at least a quantization step difference in the inputs to the first comparator stage.

REFERENCES:
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patent: 4962323 (1990-10-01), Ta
D. C. Wyland, "FET Cascade Technique Optimizes Differential Amplifier Performance", Electronics, Jan. 18, 1971, pp. 81-84.

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