Multistage logic circuit arrangement

Details Multistage logic circuit arrangement Multistage logic circuit arrangement

1979-09-21

1981-09-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, H03K 19017, H03K 19096

Patent

active

042912474

ABSTRACT:
Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.

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patent: 4040015 (1977-08-01), Fukuda
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patent: 4140927 (1979-02-01), Feucht
Lohman, "Applications of MOS FET's in Microelectronics"; SCP and Solid-State Technology; pp. 23-29; 3/1966.
MOS Integrated Circuits-Microelectronics Series-1972; "2-Phase Ratioed Logic"; p. 262.

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