Multistage interconnection network and parallel computer using t

Details Multistage interconnection network and parallel computer using t Multistage interconnection network and parallel computer using t

1996-06-14

1998-12-22

Zimmerman, Brian

Communications: electrical

Continuously variable indicating

With meter reading

34082579, 340826, 379272, H04B 338

Patent

active

058524070

ABSTRACT:
A multistage interconnection network capable of performing highly reliable communications with less hardware. In the multistage interconnection network for interconnecting a plurality of nodes, the first and final stages each have switches two times as large as the number of switches at an intermediate stage. Two output ports of each node are connected to the input ports of different first stage switches, and two input ports are connected to the output ports of final stage different switches. The input ports of switches of the intermediate stage are connected to the output ports of first stage different switches, and the output ports are connected to the input ports of final stage different switches. At least one output port of each switch at the first stage is directly connected to at least one input port of an optional switch at the final stage.

REFERENCES:
patent: 4400627 (1983-08-01), Zola
patent: 4811333 (1989-03-01), Rees
patent: 4833468 (1989-05-01), Larson et al.
patent: 4845736 (1989-07-01), Posner et al.
patent: 4952930 (1990-08-01), Franaszek et al.
patent: 5123011 (1992-06-01), Hein et al.
patent: 5175539 (1992-12-01), Richter
patent: 5287491 (1994-02-01), Hsu
patent: 5325089 (1994-06-01), Goeldner
patent: 5390178 (1995-02-01), Hunter
patent: 5396231 (1995-03-01), Hein
patent: 5408231 (1995-04-01), Bowdon
patent: 5450074 (1995-09-01), Yoshifuji
patent: 5542048 (1996-07-01), Olnowich et al.
IEEE Transactions on Computers, "Reliable Butterfly Distributed-Memory Multiprocessors", N. Tzeng, vol. 43, (1994) Sep., No. 9, New York, U.S.
Microprocessing and Microprogramming, "Hardware Features of the Static Communication Network of a Parallel Architecture", V. Neri, et al., vol. 38, No. 1/5, Amsterdam, Netherlands.
Journal of Parallel and Distributed Computer, "A Study of Permutation Networks: New Designs and Some Generalizations", A.Y. Oruc, vol. 22, No. 2, Aug. 1994, Orlando, Florida.

Affiliated with

Also associated with

Rating

Multistage interconnection network and parallel computer using t does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multistage interconnection network and parallel computer using t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multistage interconnection network and parallel computer using t will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2051171