Multistage analog-to-digital converter employing dither

Details Multistage analog-to-digital converter employing dither Multistage analog-to-digital converter employing dither

1998-02-19

2001-01-09

Pierre, Peguy Jean (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S161000

Reexamination Certificate

active

06172629

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to multistage converters and in particular to multistage analog-to-digital converters employing dither to reduce non-linearity.
BACKGROUND OF THE INVENTION
Analog-to-digital converters (ADCs) convert an analog input into a corresponding digital representation. Multiple stage ADCs include a plurality of stages, each of which contributes to the digital representation. Multistage converters receive an analog signal in a first stage for processing. The first stage determines one or more bits. A residue is generated and passed to a subsequent stage for processing to determine one or more additional bits. This process continues through each of the stages of the converter. When each stage completes processing a sample or residue, it receives a new sample or residue to process. One type of multiple stage converter is known as a pipelined converter. Pipelining causes an initial latency in computation time required to fill the pipeline, but increases the throughput of the converter due to parallel processing.
Each stage of a multistage ADC may produce more bits than the output of that stage represents in a digital representation of a sampled representation of the analog signal input to the first stage of the converter, providing some redundancy of information for error correction. Error correction may be provided to ease the precision of each stage of conversion. An error corrector receives the bits produced by each stage of the multistage converter and generates a digital output representative of the sampled analog input. The digital error corrector output is also the digital output from the converter.
Multistage converters are disclosed in various publications, including “A 10-b 20-Msample/s Analog-to-Digital Converter”, by Lewis, et al, IEEE Journal of Solid State Circuits, March 1992, Vol. 27, pp. 351-358, and Analog Integrated Circuits Design, by D. A. Johns and K. Martin, the disclosures of which are hereby incorporated by reference.
One known technique to reduce non-linearity in an analog-to-digital converters is to add random noise to the input signal. Adding random noise to the input signal reduces the signal-to-noise ratio of the converter. To reduce non-linearity without reducing the signal-to-noise ratio, random noise energy may be added to the signal in a frequency range that is not of interest. However, for this technique to be useful in a particular application, there must be a frequency range that is not of interest where the noise can be added. In applications requiring the full range of available bandwidth for a signal, this technique could not be used. Furthermore, each of these techniques reduce the dynamic range of a converter in which they are used.
What is needed is a technique to reduce non-linearity in a multistage analog-to-converter that does not significantly reduce the dynamic range of the converter. While error correction techniques corrects for some types of errors, the accuracy of the conversion would be enhanced by introduction of dither to decrease the magnitude of spurious tones in a manner that spreads the spurious tones out over a wider frequency range than they occupy absent dither. Such a technique would retain the desirable aspects of introducing dither without using a portion of the frequency spectrum or reducing dynamic range, thereby leaving the entire frequency spectrum for signal.
SUMMARY OF THE INVENTION
In accordance with the invention, a converter for converting an input signal from one form to another includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.


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David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” pp. 513-516, 523-528, published by John Wiley & Sons, Inc., 1997.

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