Patent
1993-12-06
1998-11-03
Lee, Thomas C.
395551, 39580001, 39580032, G06F 1300
Patent
active
058322531
ABSTRACT:
The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.
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King Edward C.
Scheitrum Mark E.
Smith Alan G.
CPU Technology, Inc.
Lee Thomas C.
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