Multiprocessor with split transaction bus architecture for sendi

Details Multiprocessor with split transaction bus architecture for sendi Multiprocessor with split transaction bus architecture for sendi

1995-07-24

1998-03-24

An, Meng-Ai T.

395472, 395473, 39520068, G06F 1300, G06F 1516

Patent

active

057322449

ABSTRACT:
A method of arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase, and arranged for access by a prescribed resource stage, to facilitate "RETRY", this method including; providing a Cache Tag and Address Compare,

REFERENCES:
patent: 4648030 (1987-03-01), Bomba et al.
patent: 5504874 (1996-04-01), Galles et al.
patent: 5506971 (1996-04-01), Gollette et al.
patent: 5535345 (1996-07-01), Fisch et al.
patent: 5594880 (1997-01-01), Moyer et al.

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