Boots – shoes – and leggings
Patent
1992-04-27
1996-06-04
Black, Thomas G.
Boots, shoes, and leggings
395448, 395468, 395471, 395800, 3642287, 3642419, 36424341, 3642435, 36494067, 36496431, 36496427, 364DIG1, 364DIG2, G06F 15167, G06F 1517
Patent
active
055242120
ABSTRACT:
A plurality of program processors, shared memory, dual port memory, external cache memory and a control processor form a multiprocessor system. A shared memory bus links the program processors, shared memory, dual port memory and external cache memory. Program processor I/O occurs through a pair of serial I/O channels coupled to one port of the dual port memory. A write generate mode is implemented for updating cache by first allocating lines of shared memory as write before read areas. For such lines, cache tags are updated directly on cache misses without reading from memory. A hit is forced for such line, resulting in valid data at the updated part and invalid data at the remaining portion. Thus, part of the line is written to and the rest invalidated. The invalid portions are not read, unless preceded by a write operation. The mode reduces the number of bus cycles by making write misses more efficient.
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Chen Chung-Ho
Cooper Kenneth H.
Haralick Robert M.
Johnson Robert E.
Somani Arun K.
Black Thomas G.
Choules Jack M.
Koda Steven P.
University of Washington
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