Multiprocessor system with sequential prioritized common memory

Details Multiprocessor system with sequential prioritized common memory Multiprocessor system with sequential prioritized common memory

1987-03-24

1992-04-28

Lee, Thomas C.

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3642281, 364229, 364230, 3642301, 364240, 3642412, 3642426, 3642429, 364244, 364246, 3642462, 3642468, 3649269, 36492691, 36492797, 36492792, 36493146, 3649314, 3649423, 3649426, 3649354, 36493541, 364DIG1, 364DIG2, G06F 1330, G06F 9312

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active

051093308

ABSTRACT:
In a multi-processor system in which a plurality of microprocessor systems are allocated to a common multi-processor bus in cyclical fashion in a sequence prescribed by priority characterizing numbers assigned to said systems, the priority allocation of bus access is overlaid by a further method that coordiantes the access fo a microprocessor system to a region storing a common data base in a common memory. One of the microprocessor systems functions as the main processor system and is authorized to up-date the data base and all other microprocessor systems function as subsidiary procesors which can read the data base information. Before its access, every microprocessor system accessing the data base communicates a status signal to the other micro-processor systems, this preventing the main processor system from up-dating the data base while one of the subsidiary processor systems is already reading the data base information.

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