Multiprocessor system with memory fetch buffer invoked during cr

Details Multiprocessor system with memory fetch buffer invoked during cr Multiprocessor system with memory fetch buffer invoked during cr

1988-07-21

1991-07-16

Shaw, Gareth D.

Boots, shoes, and leggings

3642281, 3642283, 3642434, 36424341, 36424343, 36424344, G06F 1300

Patent

active

050329855

ABSTRACT:
An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

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