Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1993-12-13
2002-09-17
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06453406
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed generally to data processing, and more particularly to data processing systems in the form of multiple processor units interconnected to one another by an bus means for interprocessor communication therebetween. More particularly, the invention is directed to a data processing system in which groups or sections of processors are coupled to one another by a communications link that routes messages from one processor in one section to another processor in another section.
An increasingly popular type of data processing system is one implemented with a number of individual processor units capable of operating either individually or in parallel to perform data processing tasks. This type of processing system differentiates from a network of interconnected processing systems by the fact that the individual processor units are interconnected by a bus dedicated to interprocessor communication. Examples of this form of processing system may be found in U.S. Pat. Nos. 4,228,496 and 4,888,684.
As the design of such multiprocessor data processing systems evolves, and as the technology available for that design becomes more complex, limits on the construction of such systems are encountered. One such limit involves the interprocessor bus itself. Larger multiprocessor systems are often housed in multiple cabinets of relatively large size. Since the processor units housed in each of the cabinets must be connected by the interprocessor bus, the spacing between the processor units becomes critical as a result of the electrical characteristics of the bus. Thus, for example, if the spacing between processors becomes too great, the electrical characteristics of the interprocessor bus can place severe limitation on bus speed, the number of processor units that may be connected, and the like.
Also, there are constraints upon the placement of the individual cabinets themselves.
Further, it is often true that subsequent generations of multiprocessor systems having an interprocessor bus for processor to processor communications are designed and built as technology advances. It may be desirable to intermix processor units from earlier designs with those of later designs. However, the electrical characteristics of the interprocessor bus and connection of that bus to the processor unit itself often differ from that of earlier designs, partly from use of newer technology. Thus, mixing earlier processor units with later processor units in multiprocessor system design can be prohibitive.
Thus, it is evident that some resolution to the limitations imposed upon extensions of interprocessor buses used to interconnect multiple processor units is needed.
SUMMARY OF THE INVENTION
The present invention provides a communications link, here in the form of a fiber optic interconnect system, that permits smaller groups or sections of processor units to be interconnected by an interprocessor bus (IPB) for processor to processor communication, permitting also communication with other like configured multiprocessor systems by the fiber optic interconnection system. The invention permits interprocessor communication between processors positioned at greater distances from one another than heretofore, and allows processors having different electrical and other characteristics for connection to an interprocessor bus to communicate with one another.
Broadly, the invention is directed to allocating the processor units of a multiprocessor system to sections of processor units. The processor units of each section are intercoupled by an interprocessor bus for processor-to-processor communication. Each section, in turn, is connected by a communications link so that processor units of one section can communicate with those of any other section. In the preferred embodiment of the invention, the interprocessor bus of a section is coupled to the interprocessor bus of “neighbor” sections by data transfer sections that provide the interface between the interprocessor bus of a section and the communications links. Further, the preferred implementation of the communication link between section is in the form of a bi-directional fiberoptic data path between each neighbor section.
Each bi-directional fiber optic data path is formed using a pair of optical fibers. Each data transfer section includes a pair of “channels,” one for each optical fiber. One optical fiber, and its associated channel of the data transfer section, is dedicated to communicating information packets, containing a processor message, from the fiber link to the IPB of that section; the other optical fiber, and its associated channel, is dedicated to communicating processor unit generated messages from the interprocessor bus to the fiber optic link where they are transmitted as information packets to a receiving data transfer section of a neighbor section.
Communications over the IPB between the processor units of a particular section is in the form of messages. A message, in turn, is contained in one or more multi-word data “packets” (a “word,” as used herein, is 16 bits of data). To differentiate between what is communicated on the IPB from that on the communications link, “IPB packet” will refer to what is generated by a processor unit and communicated on the IPB for receipt by a destination processor unit; “information packet” will refer to what is communicated on the communications link. An information packet will include an IPB packet.
Each data transfer section includes buffer memory for storing IPB packets (removed from the information packets that contained them when communicated on the communications link) en route to the IPB or IPB packets from the IPB to be transmitted on the outgoing fiberoptic link. The buffer memory is managed in a way that operates to ensure the sequentiality of packets. For example, since messages may comprise multiple packets, the transfer of a multi-(IPB) packet message from one (the “source”) processor unit in one section to another (the “destination”) processor unit in another section will involve multiple information packets (one for each IPB packet). When transferred from a section by a data transfer section, these information packets are stored in, and retrieved from, the buffer memory in a manner that maintains the sequence of the IPB packets as generated by the source processor unit. In a similar fashion, the sequence of received information packets is also maintained in their transfer to the interprocessor bus.
Packets received by each channel, whether from the communications link for transfer to the IPB, or from the IPB for transfer to the communications link, are each identified while resident in the data transfer section by a destination address. When received by a channel, each packet is stored in the buffer memory, at a location determined in part by the destination address, until it can be forwarded to its ultimate destination (i.e., The communications link or the IPB). The destination address is developed by the channel and temporally stored in a manner that “schedules” the corresponding packet for transmission. Subsequently, when the channel prepares to transmit the packet (onto the optical fiber or the IPB), the destination address is retrieved and used to retrieve the packet from the buffer memory. In the event that transmission is prematurely terminated, the channel will return the destination address to the temporary storage, where it resides until the packet is again to be sent.
When a packet is successfully sent onto its ultimate destination by the channel, the location it occupied in buffer memory is released; until then the location is flagged as being occupied.
Preferably, the processor units are interconnected in a ring topology so that there are two paths from a processor unit in any section to a processor unit in any other section. Each data transfer section includes a routing table that provides information as to the shortest available route to processor units of other sections.
Finally, there is included an autoconfiguration routine, and means f
Agarwala Unmesh
Comstock Charles E.
Moore Frank G.
Quan Stanley S.
Sarnikowski Scott
Compaq Computer Corporation
Follansbee John A.
Oppenheimer Wolff & Donnelly LLP
Sherry Leah
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