Excavating
Patent
1989-05-23
1991-07-16
Smith, Jerry
Excavating
371 161, G06F 1100
Patent
active
050330470
ABSTRACT:
In a multiprocessor system in which at least three processors are connected to a system bus by way of which data and source and destination processor identification numbers are exchanged between source and destination processors. A third processor receives the same data and the same source and destination processor ID numbers as those received by the destination processor. Each processor detects an error in data being transmitted to the bus and detects an error in data being received therefrom. A transmit error bit is stored into a transmit error bit register in response to the detection of error in the transmitted data and a receive error bit is stored into a receive error bit register in response to the detection of error in the received data. The processor ID numbers are also stored in registers in each processor in response to the detection of the errors. A fault locator is connected to the transmit and receive error bit registers of each processor and to the ID number registers of each processor to analyze the contents of such registers to locate a fault in the system on the basis of a majority decision.
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Chung Phung My
NEC Corporation
Smith Jerry
LandOfFree
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