Multiprocessor system having respective bus interfaces that tran

Details Multiprocessor system having respective bus interfaces that tran Multiprocessor system having respective bus interfaces that tran

1995-01-13

1996-04-30

Geckil, Mehmet

Boots, shoes, and leggings

39520021, 364DIG1, 36424294, 364239, G06F 1300

Patent

active

055133673

ABSTRACT:
A plurality of system buses are provided in association with multiple processors and a memory, respectively. Registers are provided between the system buses so that a packet signal can be sent, in a pipelined form, to bus interfaces connected to the respective system buses. Each bus interface is assigned its own ID value. Counting the number of ID values cyclically at the rise of a clock signal, each register asserts a bus-ID match signal when finding coincidence of the bus-ID value. In response to the asserting of the bus-ID match signal, the associated bus interface provides the packet signal to the system bus. When the bus-ID signal is negated, the associated bus interface takes in the packet signal from the system bus.

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Computer Architecture and Parallel Processing, McGraw-Hill, pp. 481-487.

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