Multiprocessor system having local write cache within each data

Details Multiprocessor system having local write cache within each data Multiprocessor system having local write cache within each data

1991-07-22

1994-07-05

Bowler, Alyssa H.

Boots, shoes, and leggings

395200, 395250, 395325, 395400, 395425, 364134, 364146, 3642281, 3642284, 364229, 3642306, 3642386, 364239, 364240, 3642546, 364DIG1, 364DIG2, G06F 900

Patent

active

053275705

ABSTRACT:
A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

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