Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Patent
1997-07-11
2000-10-10
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
712 29, 712 34, G06F 1516
Patent
active
061311537
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a multiprocessor system constituted by a plurality of data processors.
BACKGROUND ART
In recent years, the performance of a data processor has greatly advanced along with improvements in mainly a manufacturing process, an architecture, and the like. As a result, strong demand has arisen for advanced data processing using data processors. To meet this demand, the high-speed operation of the data processor has been requested. On the other hand, the improvements in a manufacturing process, an architecture, and the like have almost limitations, and an increase in cost due to these improvements cannot be neglected. Therefore, the development of a data processor itself is getting difficult.
Under these circumstances, a multiprocessor system is proposed by combining existing data processors. In a conventional multiprocessor system, desired data processing is distributed to and executed in a plurality of data processors connected through a single system bus constituted by an address bus, a data bus, a control bus, and the like, thereby shortening the total processing time.
In the conventional multiprocessor system, the plurality of data processors have a parallel relationship in which the system bus is shared by these data processors. For this reason, scheduling for determining the processing order of the processors must be so performed as to efficiently use the system bus by assigning to these data processors a plurality of task sets obtained by dividing the desired data processing. This scheduling is performed using an operating system inherent to the multiprocessor system.
The above multiprocessor system has the following drawback when the development of application software is restricted by the limitation of the system capacity. That is, the limitation of the system capacity can be widened when the number of processors increases. The increase in the number of processors changes the scheduling environment, requiring a new operating system program. In addition, this new operating system program often disables execution of part of existing application software. In this case, the part of the application software must be rewritten to match the new operating system program. Therefore, the expansion of the system capacity is difficult except a special application which need not consider efficient utilization of software resources.
It is an object of the present invention to provide a multiprocessor system capable of increasing the number of data processors without changing an operating system program.
DISCLOSURE OF INVENTION
According to the present invention, there is provided a multiprocessor system comprising a main memory unit for storing an application program and an operating system program, a plurality of processor units each including at least one data processor to perform distributed processing of the application program in accordance with the operating system program, a plurality of system buses connected between the plurality of processor units and the main memory unit, and a plurality of gateway units inserted in the system buses to set a hierarchical order of the main memory unit and the plurality of processor units using the main memory unit as a highest hierarchical level and allow data transmission between the hierarchical levels, the plurality of gateway units each being arranged to monitor memory access requests from hierarchical levels lower than a corresponding hierarchical level and control to hold the memory access request when the memory access request interferes with memory access from the corresponding hierarchical level.
In this multiprocessor system, the plurality of gateway units are inserted in the system buses to set a hierarchical order of the main memory unit and the plurality of processor units using the main memory unit as a highest hierarchical level and allow data transmission between the hierarchical levels, and each of the plurality of gateway units is arranged to monitor memory access requests from hierarchical levels lower
REFERENCES:
patent: 4228496 (1980-10-01), Katzman et al.
patent: 5241641 (1993-08-01), Iwasa et al.
patent: 5553240 (1996-09-01), Madduri
patent: 5689679 (1997-11-01), Jouppi
An Meng-Ai T.
Monestime Mackly
NKK Corporation
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