Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2006-09-26
2006-09-26
Pwu, Jeffrey (Department: 2143)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S231000, C709S248000, C709S223000, C710S052000, C710S056000, C719S321000
Reexamination Certificate
active
07114011
ABSTRACT:
A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.
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Buch Deep K.
Hu Zhenjun
Pentkovski Vladimir M.
Schaper Neil
Zhao David
Intel Corporation
Pwu Jeffrey
Steiner Paul E.
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