Multiprocessor programmable interrupt controller system with sep

Details Multiprocessor programmable interrupt controller system with sep Multiprocessor programmable interrupt controller system with sep

1993-12-30

1996-09-10

Ray, Gopal C.

Boots, shoes, and leggings

395741, 395868, 3642412, 3642302, 3642808, 364240, 3642402, 364 1DIG, G06F 1326, G06F 946

Patent

active

055554202

ABSTRACT:
A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.

REFERENCES:
patent: 3905025 (1975-09-01), Davis et al.
patent: 4250546 (1981-02-01), Boney et al.
patent: 4271468 (1981-06-01), Christensen et al.
patent: 4484264 (1984-11-01), Friedli et al.
patent: 4796176 (1989-01-01), D'Amico et al.
patent: 4866664 (1989-09-01), Burkhardt, Jr. et al.
patent: 4868742 (1989-09-01), Gant et al.
patent: 5123094 (1992-06-01), MacDougall
patent: 5179707 (1993-01-01), Piepho
patent: 5218703 (1993-06-01), Fleck et al.
patent: 5428794 (1995-06-01), Williams
Val Popescu et al., "The Metaflow Architecture," IEEE Micro, pp. 10-13 and 63-73 (Jun. 1991).

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