Patent
1995-07-14
1998-10-06
Butler, Dennis M.
395558, 395559, G06F 104, G06F 112
Patent
active
058190759
ABSTRACT:
A scalable coherent interface (SCI) architecture delivers a high speed unidirectional signal from one SCI node to a next successive SCI node. The signal includes a data portion, e.g., SCI symbol, and a clock portion, e.g., a symbol separator. The clock portion indicates when the data portion may be sampled when collecting a sequence of SCI symbols. Relative timing between bits of the data portion and between the data portion as a whole and the symbol separator clock becomes skewed during transmission. The receiving node introduces delay in the clock portion as a function of detected stability in a synchronizing packet. A plurality of data registers are cyclicly written in response to the delayed clock portion whereby a single one of said registers at a given time is concurrently clocked and enabled. A control device monitors enable signals applied to the registers and in coordinated fashion cyclically reads SCI symbols therefrom. As a result, signal transmission from a transmitting time domain to a receiving time domain includes a time domain mapping and de-skewing function.
REFERENCES:
patent: 5428649 (1995-06-01), Cecchi
patent: 5487092 (1996-01-01), Finney et al.
patent: 5560027 (1996-09-01), Watson et al.
Butler Dennis M.
Cushing Keith A.
Dolphin Interconnect Solutions, Inc.
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