Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-12-11
2007-12-11
Kindred, Alford (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S028000, C712S029000
Reexamination Certificate
active
10752959
ABSTRACT:
The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.
REFERENCES:
patent: 3308436 (1967-03-01), Borck et al.
patent: 4402045 (1983-08-01), Krol
patent: 5097412 (1992-03-01), Orimo et al.
patent: 5179715 (1993-01-01), Andoh et al.
patent: 5504918 (1996-04-01), Collette et al.
patent: 5606686 (1997-02-01), Tarui et al.
patent: 5671430 (1997-09-01), Gunzinger
patent: 5918249 (1999-06-01), Cox et al.
patent: 6178466 (2001-01-01), Gilbertson et al.
patent: 6205508 (2001-03-01), Bailey et al.
patent: 6246692 (2001-06-01), Dai et al.
patent: 6289021 (2001-09-01), Hesse
patent: 6421775 (2002-07-01), Brock et al.
patent: 6519649 (2003-02-01), Arimilli et al.
patent: 6519665 (2003-02-01), Arimilli et al.
patent: 6526467 (2003-02-01), Joh
patent: 6529999 (2003-03-01), Keller et al.
patent: 6591307 (2003-07-01), Arimilli et al.
patent: 6728841 (2004-04-01), Keller
patent: 6820158 (2004-11-01), Lee et al.
patent: 6848003 (2005-01-01), Arimilli et al.
patent: 6901491 (2005-05-01), Kohn et al.
patent: 2004/0088523 (2004-05-01), Kessler et al.
patent: 2004/0117510 (2004-06-01), Arimilli et al.
patent: 2005/0021699 (2005-01-01), Kola et al.
patent: 2005/0060473 (2005-03-01), Duncan et al.
patent: 2005/0091473 (2005-04-01), Aguiler et al.
Sima et al.; “Advanced Computer Architectures: A Design Space Approach”; 1998.
IBM Corporation, “Omega-Crossbar Network,” IBM Technical Disclosure Bulletin; Oct. 1, 1984; vol. 27, No. 5, p. 2811-2816.
Arimilli Ravi Kumar
Chung Vicente Enrique
Joyner Jody Bern
Lewis Jerry Don
Dillon & Yudell LLP
Geib Benjamin P.
International Business Machines - Corporation
Kindred Alford
Salys Casimer K.
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