Multiprocessor coupling system with integrated compile and run t

Details Multiprocessor coupling system with integrated compile and run t Multiprocessor coupling system with integrated compile and run t

1995-06-29

1996-11-12

Shah, Alpesh M.

Boots, shoes, and leggings

395376, 364230, 3642624, 364 1DIG, G06F 1516

Patent

active

055749399

ABSTRACT:
In a parallel data processing system, very long instruction words (VLIW) define operations able to be executed in parallel. The VLIWs corresponding to plural threads of computation are made available to the processing system simultaneously. Each processing unit pipeline includes a synchronizer stage for selecting one of the plural threads of computation for execution in that unit. The synchronizers allow the plural units to select operations from different thread instruction words such that execution of VLIWs is interleaved across the plural units. The processors are grouped in clusters of processors which share register files. Cluster outputs may be stored directly in register files of other clusters through a cluster switch.

REFERENCES:
patent: 4392200 (1983-06-01), Arulpragasam et al.
patent: 4482272 (1984-11-01), Green
patent: 4733353 (1988-04-01), Jaswa
patent: 4926323 (1990-05-01), Baror et al.
patent: 5021945 (1991-06-01), Morrison et al.
patent: 5163139 (1992-11-01), Haigh et al.
patent: 5179680 (1993-01-01), Colwell
patent: 5185878 (1993-02-01), Baror et al.
patent: 5197137 (1993-03-01), Kumar et al.
patent: 5291581 (1994-03-01), Cutler et al.
patent: 5357617 (1994-10-01), Davis et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5442762 (1995-08-01), Kato et al.
Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units, "IBM Journal, Jan. 1967, pp. 25-33.
Fisher, Joseph et al., "Very Long Instruction Word Architectures and the ELI-512, " Association for Computing Machinery, 1983, pp. 140 150.
Smith, Burton J., "Architecture and applications of the HEP multiprocessor computer system," SPIE, vol. 298 Real-Time Signal Processing IV, 1981, pp. 241-248.
Keckler, Stephen W. & Daly, William J., "Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism, " The Proceedings of the 19th Annual International Symposium on Computer Architecture, May 1992,pp. 202-213.
Kato et al., "Delayed Instruction Execution on a Long Instruction Word (LIW) Computer, "Systems and Computers in Japan, vol. 23, No. 14, 1992, pp. 13-22.
Paver et al., "Register Locking in an Asynchronous Microprocessor," 1992 IEEE International Conference on Computer Design, 11 Oct., 1992, pp. 351-355.
Lino De Campos, "Asynchronous Polycyclic Architecture, " Second Joint International Conference on Vector and Parallel Processing Conpar 92-VAPP V, Sep. 1, 1992, Lyon France Sections 2-4 & 6, pp. 387-398.
Wolf et al., "A Variable Instruction Stream Extension to the VLIW Architecture, "Computer Architeture News, vol. 19, No. 2, Apr. 1991, pp. 2-14.
"The Metaflow Lighting Chipset", COMPCON Spring '91 IEEE Computer Society Int'l Conference, Bruce D. Lightner.
"The Metaflow Architecture", IEEE Micro, Jun. 1991, Val Popesu.

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