Boots – shoes – and leggings
Patent
1996-06-12
1998-04-07
Harrity, John E.
Boots, shoes, and leggings
364229, 364DIG1, G06F 1576
Patent
active
057376280
ABSTRACT:
A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
REFERENCES:
patent: 4933933 (1990-06-01), Dally et al.
patent: 4980822 (1990-12-01), Brantley et al.
patent: 5008882 (1991-04-01), Peterson et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5117350 (1992-05-01), Parrish et al.
patent: 5134690 (1992-07-01), Samatham
patent: 5157692 (1992-10-01), Horie et al.
patent: 5170482 (1992-12-01), Shu et al.
patent: 5201044 (1993-04-01), Frey, Jr. et al.
patent: 5210705 (1993-05-01), Chauvel et al.
patent: 5218676 (1993-06-01), Ben-ayed et al.
patent: 5313645 (1994-05-01), Rolfe
patent: 5341504 (1994-08-01), Mori et al.
patent: 5383191 (1995-01-01), Hobgood et al.
patent: 5390164 (1995-02-01), Kremer
patent: 5475858 (1995-12-01), Gupta et al.
patent: 5590284 (1996-12-01), Crosetto
"Deadlock-Free Routing Schemes on Multistage Interconnection Networks", IBM Technical Disclosure Bulletin, 35, 232-233, (Dec. 1992).
Bradley R. Carlile, "Algorithms and Design: The CRAP APP Shared-Memory System", Compcon Spring '93, San Francisco, CA, 312-320, (Feb. 22, 1993).
William Dally, et al., "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computers, C-36, 547-553, (May, 1987).
William Dally, "Performance Analysis of k-ary n-cube Interconnection Networks", IEEE Transactions on Computers, 39, 775-785, (Jun., 1990).
William Dally, "Virtual-Channel Flow Control", IEEE, 60-68, (1990).
Robert Gallager, "Scale Factors for Distributed Routing Algorithms", NTC '77 Conference Record, 2, (1978).
Christopher Glass, et al., "The Turn Model for Adaptive Routing", ACM, 278-287, (1992).
Daniel Linder, et al., "An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes", IEEE Transactions on Computers, 40, 2-12, (Jan., 1991).
Peter Nuth, et al., "The J-Machine Network", IEEE, 420-423, (1992).
Domenico Talia, "Message-Routing Systems for Transputer-Based Multicomputers", IEEE MICRO, vol. 13, No. 3, New York US, 62-72, (Jun., 1993).
C. S. Yang, et al., "Performance Evaluation of Multicast Wormhole Routing in 2D-Torus Multicomputers", IEEE, 173-178, (1992).
J. Yantchev, et al., "Adaptive, Low Latency, Deadlock-Free Packet Routing for Networks of Processors", IEEE Proceedings, 136, 178-186, (May, 1989).
Birrittella Mark S.
Kessler Richard E.
Oberlin Steven M.
Passint Randal S.
Thorson Greg
Cray Research Inc.
Harrity John E.
LandOfFree
Multiprocessor computer system with interleaved processing eleme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiprocessor computer system with interleaved processing eleme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiprocessor computer system with interleaved processing eleme will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-27351