Multiprocessor computer system utilizing a tapped delay line ins

Details Multiprocessor computer system utilizing a tapped delay line ins Multiprocessor computer system utilizing a tapped delay line ins

1983-04-27

1986-03-04

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1504, G06F 1520

Patent

active

045743452

ABSTRACT:
The disclosure is directed to a multiprocessor data processing system. The data processing system of the invention generally comprises a plurality of microprocessor units and an instruction memory device electrically storing a common set of instructions in a pre-ordered sequence, each of said instructions being stored in representative, digital, electrical signal form. A tapped delay line instruction bus system is provided to electrically interconnect the instruction memory with each of the microprocessor units. The tapped delay line instruction bus system includes a plurality of individual tap buses and electrical controls operable to apply the digital electrical signals for each of the instructions stored in the instruction memory device to each of the individual tap buses, one tap bus at a time, in a timed, time-skewed sequence. Each of the plurality of microprocessor units is electrically connected to one of the individual tap buses of the tapped delay line instruction bus system whereby each of the microprocessor units receives the representative electrical signals for each of the instructions stored in the instruction memory device pursuant to a pre-ordered, timed sequence.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3573851 (1971-04-01), Watson et al.
patent: 3913070 (1975-10-01), Malcolm et al.
patent: 4059851 (1977-11-01), Nutter, Jr.
patent: 4392200 (1983-07-01), Arulpragasm et al.

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