Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1996-12-12
1999-08-03
Powell, Mark R.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 23, G06F 1577, G06F 1100
Patent
active
059319380
ABSTRACT:
Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.
REFERENCES:
patent: 5649106 (1997-07-01), Tsujimichi et al.
patent: 5680634 (1997-10-01), Estes
patent: 5689661 (1997-11-01), Hayashi et al.
patent: 5710938 (1998-01-01), Dahl et al.
patent: 5784802 (1998-07-01), Greenstein et al.
Aneshansley Nicholas E.
Drogichen Daniel P.
McCrocklin Andrew J.
Powell Mark R.
Rossi Jeffrey Allen
Sun Microsystems Inc.
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