Multiprocessor computer backplane bus in which bus transactions

Details Multiprocessor computer backplane bus in which bus transactions Multiprocessor computer backplane bus in which bus transactions

1995-11-15

1996-12-03

Ray, Gopal C.

395730, 395729, 395293, 395728, G06F 1336

Patent

active

055817130

ABSTRACT:
A computer having multiple modules connected by a backplane bus includes multiple competition signal lines and multiple class signal lines. Access to the backplane bus to engage in one or more of multiple types of bus transactions is arbitrated between the modules by classifying the bus transactions into different classes and, during each of a succession of competition cycles, when a module wants access to the backplane bus to engage in a particular type of bus transaction, asserting a class signal line corresponding to a class in which the particular type of bus transaction has been classified. Based on information presented on the class signal lines, it is determined which modules are or are not eligible to compete for access to the backplane bus. When a module is eligible to compete for access to the backplane bus, it drives an identification code associated with the module on the competition signal lines. Then, based on information presented on the competition signal lines, a module is granted access to the backplane bus.

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